The present invention relates to techniques for debugging hard intellectual property blocks, and more particularly, to techniques for accessing various internal signals of a hard intellectual property block.
Programmable logic devices (PLDs) are a type of programmable logic integrated circuit. Programmable logic integrated circuits can be configured to perform a variety of logical user functions. Programmable logic integrated circuits also include field programmable gate arrays (FPGAs), programmable logic arrays, configurable logic arrays, etc.
PLDs typically have numerous logic blocks that can be configured to implement various combinatorial and sequential functions. The logic blocks have access to a programmable interconnect structure. The programmable interconnect structure can be programmed to interconnect the logic blocks in almost any desired configuration. Many of today's PLDs have on-chip non-programmable application specific integrated circuit (ASIC) blocks. The ASIC blocks are also referred to as hard intellectual property (HIP) blocks.
A HIP block embedded in PLD is very difficult to hardware debug as internal signals of the HIP block cannot be directly probed. To provide access to internal signals, one conventional technique dedicates input/output (I/O) pins of the HIP block to key internal signals. However, many of these dedicated I/O pins become unnecessary after completion of design verification. Thus, during normal operation, a significant number of the limited I/O pins of the HIP block are squandered.
Therefore, it would be desirable to provide improved techniques to debug a HIP block by monitoring internal signals and states of the HIP block.